Presentation 2007-03-09
A Method to Evaluate Logic Functions Based On Decision Diagram Using Memory Packing
Hiroyuki TANAKA, Hiroki NAKAHARA, Munehiro MATSUURA, Tsutomu SASAO,
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Abstract(in English) This paper proposes a method to evaluate logic functios using decision diagrams. Quasi-Reduced Multi-valued Decision Diagrams(QRMDDs) are used for logic simulation. This paper also shows a method to reduce memory requirement and computation time by memory packing. The speedup is due to the reduction of cache miss.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) QRMDD / memory packing
Paper # VLD2006-148,ICD2006-239
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Conference Date 2007/3/2(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) A Method to Evaluate Logic Functions Based On Decision Diagram Using Memory Packing
Sub Title (in English)
Keyword(1) QRMDD
Keyword(2) memory packing
1st Author's Name Hiroyuki TANAKA
1st Author's Affiliation Program of Creation Informatics, Kyushu Institute of Technology()
2nd Author's Name Hiroki NAKAHARA
2nd Author's Affiliation Program of Creation Informatics, Kyushu Institute of Technology
3rd Author's Name Munehiro MATSUURA
3rd Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology
4th Author's Name Tsutomu SASAO
4th Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology
Date 2007-03-09
Paper # VLD2006-148,ICD2006-239
Volume (vol) vol.106
Number (no) 552
Page pp.pp.-
#Pages 6
Date of Issue