Presentation 2007/3/2
Easily Testable Multiplier with 4-2 Adder Tree
Nobutaka KITO, Kensuke HANAI, Naofumi TAKAGI,
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Abstract(in English) The growth of the scale of VLSI designs makes test cost of VLSI chips expensive. Techniques of test cost reduction are required. A multiplier with a 4-2 adder tree, which is fast and has simple VLSI layout, is useful for a high-speed datapath. We present an easily testable multiplier with a 4-2 adder tree, with respect to the Cell Fault Model (CFM). We treat full adders as cells. We demonstrate a 4-2 adder tree, which has recursive configuration by unificating connection manner between 4-2 adders, has a test set which is derived recursively and whose size is independent of depth of the tree. Also, we demonstrate a design method of a partial product generation circuit to test a 4-2 adder tree through it.
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Keyword(in English) test generation / multiplier / C-testability / 4-2 adder tree
Paper # VLD2006-104,ICD2006-231
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Conference Date 2007/3/2(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Easily Testable Multiplier with 4-2 Adder Tree
Sub Title (in English)
Keyword(1) test generation
Keyword(2) multiplier
Keyword(3) C-testability
Keyword(4) 4-2 adder tree
1st Author's Name Nobutaka KITO
1st Author's Affiliation Graduate School of Information Science, Nagoya University()
2nd Author's Name Kensuke HANAI
2nd Author's Affiliation Graduate School of Information Science, Nagoya University
3rd Author's Name Naofumi TAKAGI
3rd Author's Affiliation Graduate School of Information Science, Nagoya University
Date 2007/3/2
Paper # VLD2006-104,ICD2006-231
Volume (vol) vol.106
Number (no) 552
Page pp.pp.-
#Pages 6
Date of Issue