| Presentation | 2007-03-08 Design Method of Radix Converters Using Arithmetic Decompositions(3) Yukihiro IGUCHI, Tsutomu SASAO, Munehiro MATSUURA, Toshikazu AOYAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance, decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. Design methods for binary to q-nary converters were presented by us. It introduced a new design technique based on weighted-sum (WS) functions. We compute a WS function for each digit by an LUT cascade and a binary adder, then add adjacent digits with q-nary adders. We developed a synthesis tool which produces Verilog-HDL files and data patterns of embedded memories on FPGAs. A 16-bit binary to decimal converter is designed to show the tool. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Radix converter / Multiple valued logic / LUT cascades |
| Paper # | VLD2006-135,ICD2006-226 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Method of Radix Converters Using Arithmetic Decompositions(3) |
| Sub Title (in English) | |
| Keyword(1) | Radix converter |
| Keyword(2) | Multiple valued logic |
| Keyword(3) | LUT cascades |
| 1st Author's Name | Yukihiro IGUCHI |
| 1st Author's Affiliation | Department of Computer Science, Meiji University() |
| 2nd Author's Name | Tsutomu SASAO |
| 2nd Author's Affiliation | Department of Computer Science and Electronics, Kyushu Institute of Technology |
| 3rd Author's Name | Munehiro MATSUURA |
| 3rd Author's Affiliation | Department of Computer Science and Electronics, Kyushu Institute of Technology |
| 4th Author's Name | Toshikazu AOYAMA |
| 4th Author's Affiliation | Department of Computer Science, Meiji University |
| Date | 2007-03-08 |
| Paper # | VLD2006-135,ICD2006-226 |
| Volume (vol) | vol.106 |
| Number (no) | 551 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |