Presentation 2007-03-08
A CAM Emulator Using Look-Up Table Cascades
Hiroki NAKAHARA, Tsutomu SASAO, Munehiro MATSUURA,
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Abstract(in English) An address table relates k different registered vectors to the addressed from 1 to k. An address generation function represents the address table. This paper presents a realization of an address generation function with an LUT cascade on an FPGA. The address generation function is implemented by BRAMs of an FPGA, while the addition and the deletion of registered vectors are implemented by an embedded processor on the FPGA. Compared with CAMs produced by the Xilinx Core Generator, our implementations are smaller and faster. This paper also shows that the addition and deletion of a registered vector can be done in a time that is proportional to the number of cells in the LUT cascade.
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Keyword(in English) CAM / LUT cascade
Paper # VLD2006-134,ICD2006-225
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Conference Date 2007/3/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A CAM Emulator Using Look-Up Table Cascades
Sub Title (in English)
Keyword(1) CAM
Keyword(2) LUT cascade
1st Author's Name Hiroki NAKAHARA
1st Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology()
2nd Author's Name Tsutomu SASAO
2nd Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology
3rd Author's Name Munehiro MATSUURA
3rd Author's Affiliation Department of Computer Science and Electronics, Kyushu Institute of Technology
Date 2007-03-08
Paper # VLD2006-134,ICD2006-225
Volume (vol) vol.106
Number (no) 551
Page pp.pp.-
#Pages 6
Date of Issue