Presentation 2007-03-08
Low Power and High Speed Clock Distribution Technique fo 90-nm CMOS LSIs
Yousuke Hahiwara, Suguru Nagayama, Nobuaki Kobayashi, Tadayoshi Enomoto,
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Abstract(in English) The power dissipation (P_T) and delay time (t_T) of CMOS clock circuit, that consisted of a clock driver and register array modules, was minimized. The CMOS clock driver, whose fan-outs was given by x^ where x is number of parallel inverter, was exaamined using a 90-nm CMOS technology. The minimum P_T and t_T were obtained at x ranges of 3 to 9, and at x of 3 and 4, respectively. The CMOS register array module was also designed using the 90-nm CMOS technology and consisted of a single inverter pre-driver stage, two m-parallel inverter driver stages (m=1~M) and register array stage consisting of M flip flops (FFs). A single inverter in the driver stage drives M/m FFs. The minimum P_T and t_T were simultaneously obtained at m of about 1.5×M^<1/2>. Measured results agreed well with these SPICE simulated results. The P_T, t_T of the CMOS clock circuits with 41K FFs were reduced to 55%, 40% that of the conventional clock circuits, respectively.
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Keyword(in English) clock driver / register / CMOS / active power / delay-time
Paper # VLD2006-128,ICD2006-219
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Conference Date 2007/3/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Low Power and High Speed Clock Distribution Technique fo 90-nm CMOS LSIs
Sub Title (in English)
Keyword(1) clock driver
Keyword(2) register
Keyword(3) CMOS
Keyword(4) active power
Keyword(5) delay-time
1st Author's Name Yousuke Hahiwara
1st Author's Affiliation Graduate School of Science and Engineering, Chuo University()
2nd Author's Name Suguru Nagayama
2nd Author's Affiliation Graduate School of Science and Engineering, Chuo University
3rd Author's Name Nobuaki Kobayashi
3rd Author's Affiliation Graduate School of Science and Engineering, Chuo University
4th Author's Name Tadayoshi Enomoto
4th Author's Affiliation Graduate School of Science and Engineering, Chuo University
Date 2007-03-08
Paper # VLD2006-128,ICD2006-219
Volume (vol) vol.106
Number (no) 551
Page pp.pp.-
#Pages 6
Date of Issue