Presentation | 2007-03-08 Low Power and High Speed Clock Distribution Technique fo 90-nm CMOS LSIs Yousuke Hahiwara, Suguru Nagayama, Nobuaki Kobayashi, Tadayoshi Enomoto, |
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PDF Download Page | PDF download Page Link |
Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The power dissipation (P_T) and delay time (t_T) of CMOS clock circuit, that consisted of a clock driver and register array modules, was minimized. The CMOS clock driver, whose fan-outs was given by x^ |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | clock driver / register / CMOS / active power / delay-time |
Paper # | VLD2006-128,ICD2006-219 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2007/3/1(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Low Power and High Speed Clock Distribution Technique fo 90-nm CMOS LSIs |
Sub Title (in English) | |
Keyword(1) | clock driver |
Keyword(2) | register |
Keyword(3) | CMOS |
Keyword(4) | active power |
Keyword(5) | delay-time |
1st Author's Name | Yousuke Hahiwara |
1st Author's Affiliation | Graduate School of Science and Engineering, Chuo University() |
2nd Author's Name | Suguru Nagayama |
2nd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
3rd Author's Name | Nobuaki Kobayashi |
3rd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
4th Author's Name | Tadayoshi Enomoto |
4th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
Date | 2007-03-08 |
Paper # | VLD2006-128,ICD2006-219 |
Volume (vol) | vol.106 |
Number (no) | 551 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |