Presentation 2007-03-08
A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits
Yousuke HARADA, Hiroyoshi HASHIMOTO, Yukihide KOHIRA, Atsushi TAKAHASHI,
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Abstract(in English) General-synchronous circuits, in which clock is inputted to each register at an appropriate timing, are expected to achieve the higher performance than the conventional circuits. However, high-performance general-synchronous circuits are not easy to design by using the current design environment. In this paper, we propose a design methodology of general-synchronous circuits that utilizes the widely-used current CAD tools. In the proposed design methodology, a circuit is obtained from a conventional circuit by modifying clock tree. In the proposed design methodology, first, in order to reduce the clock-tree size while maintaining the achievable clock period, registers are divided into clusters by using layout information where registers in a cluster are driven by a clock buffer. The method is enhanced from the conventional one so that intra-cluster delays are taken into account. Next, a clock tree that provides clock to each cluster is constructed. The clock tree topology is determined by top-down manner by using timing information. Then, clock timings are adjusted by buffer insertion and resizing. in experiment in which a MIPS32 compatible processor is designed, it is confirmed that a clock tree layout is obtained by using CAD tools which is 8% faster than the conventional sychronous circuit and which achieves almost theoretical minimum clock period.
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Keyword(in English) general-synchronous circuit / clock schedule / cluster / clock-tree synthesis
Paper # VLD2006-127,ICD2006-218
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Conference Date 2007/3/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Clock Tree Synthesis Method by Using CAD Tools for General-synchronous Circuits
Sub Title (in English)
Keyword(1) general-synchronous circuit
Keyword(2) clock schedule
Keyword(3) cluster
Keyword(4) clock-tree synthesis
1st Author's Name Yousuke HARADA
1st Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology()
2nd Author's Name Hiroyoshi HASHIMOTO
2nd Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology
3rd Author's Name Yukihide KOHIRA
3rd Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology
4th Author's Name Atsushi TAKAHASHI
4th Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology
Date 2007-03-08
Paper # VLD2006-127,ICD2006-218
Volume (vol) vol.106
Number (no) 551
Page pp.pp.-
#Pages 5
Date of Issue