Presentation	2007-03-08 A 90-nm SRAM for Video Signal processors implementing Dynamic Voltage and Frequency Scaling Takeshi Iwanari, Nobuaki Kobayashi, Tadayoshi Enomoto,
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Abstract(in English)	A low power 90-nm CMOS 2K-bit SRAM was developed. This SRAM implemented a self-controllable voltage level (SVL) circuit-which can supply warious DC voltages on requests. The SVL circuit has 4 active modes and one stand-by mode. The highest operation frequencies(f_) for each active mode at V_ of 1.0V were 913NHZ, 255MHz and 47MHz, respectively. Corresponding active powers (P_) of the SRAM were 4,106μW, 1,113μW and 104μW, which were 79.2%, 43.5%, 37.2% and 28.8% of the conventional SRAM at corresponding f_s. Moreover, the stand-by power (P_) of the SRAM was 1.4μW that is 4.9% of conventional SRAM. The area overhead of the SVL circuit was only 1.5%.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	CMOS / leakage current / power dissipation / Self-controllable Voltage Level (SVL) Circuit / SRAM
Paper #	VLD2006-125,ICD2006-216
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Conference Information
Committee	ICD
Conference Date	2007/3/1(1days)
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Paper Information
Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A 90-nm SRAM for Video Signal processors implementing Dynamic Voltage and Frequency Scaling
Sub Title (in English)
Keyword(1)	CMOS
Keyword(2)	leakage current
Keyword(3)	power dissipation
Keyword(4)	Self-controllable Voltage Level (SVL) Circuit
Keyword(5)	SRAM
1st Author's Name	Takeshi Iwanari
1st Author's Affiliation	Graduate School of Science and Engineering, Chuo University()
2nd Author's Name	Nobuaki Kobayashi
2nd Author's Affiliation	Graduate School of Science and Engineering, Chuo University
3rd Author's Name	Tadayoshi Enomoto
3rd Author's Affiliation	Graduate School of Science and Engineering, Chuo University
Date	2007-03-08
Paper #	VLD2006-125,ICD2006-216
Volume (vol)	vol.106
Number (no)	551
Page	pp.pp.-
#Pages	6
Date of Issue