| Presentation | 2007-03-08 A Data Cache Optimization System for Application Processor Cores and Its Experimental Evaluations Kazuhisa HORIUCHI, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Microprocessor cores are increasingly being used in embedded systems. One major factor in improving the performance of these emvedded processors is the use of data and instruction caches. In this paper, we propose a cache architecture optimization system to select a suitable cache architecture from various candidate cache types. Our cache architecture optimization system is composed of a cache performance estimation and a cache architecture optimization algorithm. First, the cache architecture estimation obtains a total memory access time of each cache architecture. And then among the results, the cache architecture optimization algorithm selects the best cache type, cahce size, and the block size for a targeted application. Using the proposed cache architecture optimization system, we can obtain cache architectures with smaller area and simpler cache type under the same memory access time constraint. We demonstrate the feasibility of our approach by applying it to a JPEG encoder. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | data cache / cache optimization / embedded system / processor core |
| Paper # | VLD2006-122,ICD2006-213 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Data Cache Optimization System for Application Processor Cores and Its Experimental Evaluations |
| Sub Title (in English) | |
| Keyword(1) | data cache |
| Keyword(2) | cache optimization |
| Keyword(3) | embedded system |
| Keyword(4) | processor core |
| 1st Author's Name | Kazuhisa HORIUCHI |
| 1st Author's Affiliation | Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Shunitsu KOHARA |
| 2nd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2007-03-08 |
| Paper # | VLD2006-122,ICD2006-213 |
| Volume (vol) | vol.106 |
| Number (no) | 551 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |