Presentation 2007-03-08
SIMD Instructions Generation Algorithm for Multi Loop for SIMD Processor Cores Optimum Design
Hiroki NAKAJIMA, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) The hardware/software cosynthesis system named SPADES which synthesize a processor with packed SIMD type instructions needs a parallelizing compiler for the processor with packed SIMD type instructions. The parallelizing compiler targets the virtual processor that has all available hardware units. It exploits instruction level parallelism using packed SIMD type instructions and output fastest scheduled assembly codes. The output of the parallelizing compiler decides the initial configuration of the processor. This paper proposes a parallelizing algorithm for multi loop and packed SIMD instruciton generation algorithm. The proposed algorithm extracts instruction level parallelism from multi loop in input application and enables to generate packed SIMD type instructions. Experimental results show effectiveness of the proposed algorithm.
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Keyword(in English) hardware/software cosynthesis / packed SIMD type instructions / compiler / embedded processor
Paper # VLD2006-121,ICD2006-212
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Conference Date 2007/3/1(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) SIMD Instructions Generation Algorithm for Multi Loop for SIMD Processor Cores Optimum Design
Sub Title (in English)
Keyword(1) hardware/software cosynthesis
Keyword(2) packed SIMD type instructions
Keyword(3) compiler
Keyword(4) embedded processor
1st Author's Name Hiroki NAKAJIMA
1st Author's Affiliation Dept. of Computer Science, Waseda University()
2nd Author's Name Shunitsu KOHARA
2nd Author's Affiliation Dept. of Computer Science, Waseda University
3rd Author's Name Nozomu TOGAWA
3rd Author's Affiliation Dept. of Computer Science, Waseda University
4th Author's Name Masao YANAGISAWA
4th Author's Affiliation Dept. of Computer Science, Waseda University
5th Author's Name Tatsuo OHTSUKI
5th Author's Affiliation Dept. of Computer Science, Waseda University
Date 2007-03-08
Paper # VLD2006-121,ICD2006-212
Volume (vol) vol.106
Number (no) 551
Page pp.pp.-
#Pages 6
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