| Presentation | 2007-03-08 A Hardware/Software Partitioning Framework for SIMD Processor Cores Masataka OHIGASHI, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes a hardware/software(HW/SW) partitioning framework for HW/SW cosynthesis system named SPADES. SPADES is a system to synthesis processor core specialized in application automatically. Synthesized processor core would be just enough in area and performance. A HW/SW partitoner, a core part in SPADES, first decides hardware constructions which enables to process application with all speed. And then reduces hardware units (functional units, registers, and so on) to explore optimum hardware constructions. Proposal framework enables to explore optimum hardware constructions and to synthesis much smaller SIMD processor core specialized in application. In addition, because of proposal framework is divided as modules, it enables to change or extend the system without difficulty. The experimental results show effectiveness of the proposed framework. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | hardware/sofrware cosynthesis / hardware/software partitioning / framework / processor core / packed SIMD type instructions |
| Paper # | VLD2006-120,ICD2006-211 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Hardware/Software Partitioning Framework for SIMD Processor Cores |
| Sub Title (in English) | |
| Keyword(1) | hardware/sofrware cosynthesis |
| Keyword(2) | hardware/software partitioning |
| Keyword(3) | framework |
| Keyword(4) | processor core |
| Keyword(5) | packed SIMD type instructions |
| 1st Author's Name | Masataka OHIGASHI |
| 1st Author's Affiliation | Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Shunitsu KOHARA |
| 2nd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2007-03-08 |
| Paper # | VLD2006-120,ICD2006-211 |
| Volume (vol) | vol.106 |
| Number (no) | 551 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |