| Presentation | 2007-03-08 A Processing Unit Optimization Algorithm in SIMD Processor Cores Design Hiroyuki SHIGETA, Shunitsu KOHARA, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Processor cores which process image and sound data can achieve higher speed, smaller area and lower power than general-purpose processor by adding operation units specialized in application. We call these operation units "processing units". Because it takes a long time to design processing units depending on applications, a system to synthesis processing units automatically is required. This paper proposes an algorithm to optimize porcessing units for SIMD-type processor core. Our propsal synthesizes processing units automatically by clustering arithmatic and logic operation nodes from application control data flow graph(CDFG). Synthesized processing units are embedded to the prcessor core. And then we tried to explorer optimum hardware architecture by reconstructing processing units simultaneously witn processor cores. The experimental results show effectiveness of the proposed algorithm. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | operation unit optimization / hardware/software cosynthesis / processor core synthesis |
| Paper # | VLD2006-119,ICD2006-210 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/3/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Processing Unit Optimization Algorithm in SIMD Processor Cores Design |
| Sub Title (in English) | |
| Keyword(1) | operation unit optimization |
| Keyword(2) | hardware/software cosynthesis |
| Keyword(3) | processor core synthesis |
| 1st Author's Name | Hiroyuki SHIGETA |
| 1st Author's Affiliation | Dept. of Computer Science, Waseda University() |
| 2nd Author's Name | Shunitsu KOHARA |
| 2nd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Computer Science, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science, Waseda University |
| Date | 2007-03-08 |
| Paper # | VLD2006-119,ICD2006-210 |
| Volume (vol) | vol.106 |
| Number (no) | 551 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |