| Presentation | 2007-03-07 A study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits Masaki YAMAGUCHI, Yuan YANG, Ryota SAKAMOTO, Masanori MUROYAMA, Tohru ISHIHARA, Hiroto YASUURA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the transistor size shrinks, process variations increase. Under the existance of the variations, an existing design flow will not be effective for minimizing the worst-case circuit delay and average power consumption. As the first step toward developing a better solution, this paper investigates basic characteristics of the delay/power variation. We measured delay/power consumption values for 5 kinds of ring oscillator circuits with some gate depth/width designed with 90nm CMOS technology. We analyzed delay/power variations dependence on gate depth/width. The measurement results demonstrated that delay variations can be suppressed by increasing tne number of gate steps and showed that delay/power variations increase by enlarging gate width. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay Variation / Power Variation / Deep Sub-Micron / CMOS |
| Paper # | VLD2006-118,ICD2006-209 |
| Date of Issue |
| Conference Information | |
| Committee | ICD |
|---|---|
| Conference Date | 2007/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A study of Dependence on Gate Depth/Width for Analyzing Delay/Power Variations in 90nm CMOS Circuits |
| Sub Title (in English) | |
| Keyword(1) | Delay Variation |
| Keyword(2) | Power Variation |
| Keyword(3) | Deep Sub-Micron |
| Keyword(4) | CMOS |
| 1st Author's Name | Masaki YAMAGUCHI |
| 1st Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Yuan YANG |
| 2nd Author's Affiliation | School of Automation and Information Engineering, Xi'an University of Technology |
| 3rd Author's Name | Ryota SAKAMOTO |
| 3rd Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| 4th Author's Name | Masanori MUROYAMA |
| 4th Author's Affiliation | System LSI Research Center, Kyushu University |
| 5th Author's Name | Tohru ISHIHARA |
| 5th Author's Affiliation | System LSI Research Center, Kyushu University |
| 6th Author's Name | Hiroto YASUURA |
| 6th Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2007-03-07 |
| Paper # | VLD2006-118,ICD2006-209 |
| Volume (vol) | vol.106 |
| Number (no) | 550 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |