| Presentation | 2007-03-07 A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits Ryota SAKAMOTO, Masanori MUROYAMA, Tohru ISHIHARA, Hiroto YASUURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | With the shrinking of transistors, yield degradation caused by process variations become a serious problem. The gate sizing technique for minimizing the average delay time of the circuits was used so far. The ratio to the total number of the chips of the chips that fill the demanded delay time is defined as the timing yield, and we propose a new gate sizing technique to maximize the timing yield. We confirmed that when using conventional technique, the gate size is enlarged always by a constant magnification, while when using proposed technique, magnification is different depending on the load capacitance and target delay time. In addition, it was confirmed that it was effective in the improvement of the timing yield. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay Variation / Timing Yield / CMOS Circuits / Gate Sizing |
| Paper # | VLD2006-117,ICD2006-208 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Gate Sizing Technique for Maximizing Timing Yield of CMOS Circuits |
| Sub Title (in English) | |
| Keyword(1) | Delay Variation |
| Keyword(2) | Timing Yield |
| Keyword(3) | CMOS Circuits |
| Keyword(4) | Gate Sizing |
| 1st Author's Name | Ryota SAKAMOTO |
| 1st Author's Affiliation | Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University() |
| 2nd Author's Name | Masanori MUROYAMA |
| 2nd Author's Affiliation | System LSI Research Center, Kyushu University |
| 3rd Author's Name | Tohru ISHIHARA |
| 3rd Author's Affiliation | System LSI Research Center, Kyushu University |
| 4th Author's Name | Hiroto YASUURA |
| 4th Author's Affiliation | Graduate School of Information Science and Electrical Engineering, Kyushu University |
| Date | 2007-03-07 |
| Paper # | VLD2006-117,ICD2006-208 |
| Volume (vol) | vol.106 |
| Number (no) | 550 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |