| Presentation | 2007-03-07 Specification description and verification methods for IPs of Hardware design Yuji ISHIKAWA, SeongWoon KANG, Yeonbok LEE, GiLark PARK, Shota WATANABE, Kenshu SETO, Satoshi KOMATSU, Hirofumi HAMAMURA, Masahiro FUJITA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the field of electronics device design, it is required to shorten design period to put products into the market earlier. To satisfy this requirement, a design method which reuses existing designscan be very effective. In reuse based design method, a database of existing designs and description methods for specifications of existing designs play an important role. In this paper we propose a specification method to help designers understand specifications of the circuit blocks. The proposed specification description is composed of XML-based table-like enumeration of information and UML diagrams. We also propose a rule-based verification method to reduce errors in the specification description. As a case study, we made specification descriptions of circuit blocks in a control circuit of a robot. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design reuse / Specification description / Rule-based verification |
| Paper # | VLD2006-113,ICD2006-204 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Specification description and verification methods for IPs of Hardware design |
| Sub Title (in English) | |
| Keyword(1) | Design reuse |
| Keyword(2) | Specification description |
| Keyword(3) | Rule-based verification |
| 1st Author's Name | Yuji ISHIKAWA |
| 1st Author's Affiliation | Department of Electronics Engineering, School of Engineering, University of Tokyo() |
| 2nd Author's Name | SeongWoon KANG |
| 2nd Author's Affiliation | Samsung Electronics Co., Ltd. |
| 3rd Author's Name | Yeonbok LEE |
| 3rd Author's Affiliation | Department of Electronics Engineering, School of Engineering, University of Tokyo |
| 4th Author's Name | GiLark PARK |
| 4th Author's Affiliation | Samsung Electronics Co., Ltd. |
| 5th Author's Name | Shota WATANABE |
| 5th Author's Affiliation | Department of Electronics Engineering, School of Engineering, University of Tokyo |
| 6th Author's Name | Kenshu SETO |
| 6th Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 7th Author's Name | Satoshi KOMATSU |
| 7th Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| 8th Author's Name | Hirofumi HAMAMURA |
| 8th Author's Affiliation | Samsung Electronics Co., Ltd. |
| 9th Author's Name | Masahiro FUJITA |
| 9th Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 2007-03-07 |
| Paper # | VLD2006-113,ICD2006-204 |
| Volume (vol) | vol.106 |
| Number (no) | 550 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |