| Presentation | 2007-03-07 Design Checker for System-Level Design using Extended System Dependence Graph Daisuke ANDO, Takeshi MATSUMOTO, Tasuku NISHIHARA, Masahiro FUJITA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In designing system LSI or System-om-a-Chip (SoC), it is essential to find and correct design errors as early design stages as possible. In this paper, we refine the system dependence graph of SpecC, which is a C-based system-level description language, by introducing two kinds of dependence edges related to concurrency. Then, we propose a design checker which can statically detect deadlocks and race conditions as design errors by analyzing dependences on the extended system dependence graph. The preliminary experimental results show that our method can detect design errors that cannot be detected by the previous method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Design Checker / System Dependence Graph / Dependence Analysis / System-Level Design |
| Paper # | VLD2006-112,ICD2006-203 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Checker for System-Level Design using Extended System Dependence Graph |
| Sub Title (in English) | |
| Keyword(1) | Design Checker |
| Keyword(2) | System Dependence Graph |
| Keyword(3) | Dependence Analysis |
| Keyword(4) | System-Level Design |
| 1st Author's Name | Daisuke ANDO |
| 1st Author's Affiliation | Department of Electronics Engineering, University of Tokyo() |
| 2nd Author's Name | Takeshi MATSUMOTO |
| 2nd Author's Affiliation | Department of Electronics Engineering, University of Tokyo |
| 3rd Author's Name | Tasuku NISHIHARA |
| 3rd Author's Affiliation | Department of Electronics Engineering, University of Tokyo |
| 4th Author's Name | Masahiro FUJITA |
| 4th Author's Affiliation | VLSI Design and Education Center, University of Tokyo |
| Date | 2007-03-07 |
| Paper # | VLD2006-112,ICD2006-203 |
| Volume (vol) | vol.106 |
| Number (no) | 550 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |