Presentation | 2007-03-07 A 90-nm CMOS Motion Estimation Processor for MPEG4 implementing Dynamic Voltage and Frequency Scaling Yugo Ishikawa, Tatsuya Kaneko, Takeshi Iwanari, Hiroaki Nakayama, Toshihiro Tsutsui, Yosuke Hagiwara, Nobuaki Kobayashi, Tadayoshi Enomoto, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | A motion estimation (ME) processor that employs dynamic voltage and frequency scaling (DVFS) was developed using a 90-nm CMOS technology. To fully use an advantage of DVFS we developed a fast motion estimation algorithm that was called adaptively assigned breaking-off condition search (A^2BCS). The A^2BCS algorithm can calculate the amount of signal processing from which the minimum clock frequency and corresponding the minimum supply voltage are estimated. The ME processor, that consists of absolute difference accumulator, a minimum value detector, a DVFS controller, PLL clock generator and a small DC/DC converter, occupies a 330 μm×970 μm silicon area. Power dissipation of the ME processor varies from 17.33 to 44.32 μW depending on test video pictures that was from 7.11 to 17.42% power dissipation of a conventional ME processor. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Motion Estimation / absolute difference accumulator / power dissipation / dynamic voltage and frequency scaling / DC/DC converter |
Paper # | VLD2006-110,ICD2006-201 |
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Conference Information | |
Committee | ICD |
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Conference Date | 2007/2/28(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | Integrated Circuits and Devices (ICD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A 90-nm CMOS Motion Estimation Processor for MPEG4 implementing Dynamic Voltage and Frequency Scaling |
Sub Title (in English) | |
Keyword(1) | Motion Estimation |
Keyword(2) | absolute difference accumulator |
Keyword(3) | power dissipation |
Keyword(4) | dynamic voltage and frequency scaling |
Keyword(5) | DC/DC converter |
1st Author's Name | Yugo Ishikawa |
1st Author's Affiliation | Graduate School of Science and Engineering, Chuo University() |
2nd Author's Name | Tatsuya Kaneko |
2nd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
3rd Author's Name | Takeshi Iwanari |
3rd Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
4th Author's Name | Hiroaki Nakayama |
4th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
5th Author's Name | Toshihiro Tsutsui |
5th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
6th Author's Name | Yosuke Hagiwara |
6th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
7th Author's Name | Nobuaki Kobayashi |
7th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
8th Author's Name | Tadayoshi Enomoto |
8th Author's Affiliation | Graduate School of Science and Engineering, Chuo University |
Date | 2007-03-07 |
Paper # | VLD2006-110,ICD2006-201 |
Volume (vol) | vol.106 |
Number (no) | 550 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |