| Presentation | 2007-03-07 CMOS On-Chip Rat-Race Balun with Impedance Matching Naoki KOBAYASHI, Minoru FUJISHIMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | It is difficult to realize on chip baluns because the ports are not standardized by 500Ω on a chip and the area grows too much. To achieve small size on chip rat-race baluns for CMOS process with an impedance matching characteristic, rat-race baluns used transmission lines with high effect of wavelength reduction are optimized. The area of the ring part laid out as a square is reduced by 88% compared with the case to use microstrip lines when standard impedance is not 50Ω. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Impedance Matching / Rat-Race Balun / CMOS |
| Paper # | VLD2006-106,ICD2006-197 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2007/2/28(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | CMOS On-Chip Rat-Race Balun with Impedance Matching |
| Sub Title (in English) | |
| Keyword(1) | Impedance Matching |
| Keyword(2) | Rat-Race Balun |
| Keyword(3) | CMOS |
| 1st Author's Name | Naoki KOBAYASHI |
| 1st Author's Affiliation | School of Frontier Sciences, The University of Tokyo() |
| 2nd Author's Name | Minoru FUJISHIMA |
| 2nd Author's Affiliation | School of Frontier Sciences, The University of Tokyo |
| Date | 2007-03-07 |
| Paper # | VLD2006-106,ICD2006-197 |
| Volume (vol) | vol.106 |
| Number (no) | 550 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |