| Presentation | 2007-02-01 Study on A Novel Logic-Circuit Implementation Scheme Utilizing Topological Affinity between Decision-Diagram Representation of Logic Functions and Nanowire Network Structures Seiya KASAI, Tatsuya NAKAMURA, Yuta SHIRATORI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This report presents study on a novel scheme to implement logic information processing function on nanowire network structures that can be produced with various materials. Decision diagram (DD) technique make it possible to visualize logic functions by directed graphs. By combination of the logic graph and nanowire-network structures thorough their topologies, the logic function can be implemented on the nanowire network directly. Its logic operation is realized by gate control of transport of information messengers in the nanowire. We demonstrate this approach by the hardware implementation of circuits, where GaAs-based etched nanowire networks are controlled by nanometer-scale Schottky wrap gates. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Logic circuit / nanodevice / nanowire network / decision diagram (DD) / Schottky wrap gate (WPG) |
| Paper # | ED2006-245,SDM2006-233 |
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| Conference Information | |
| Committee | ED |
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| Conference Date | 2007/1/25(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Electron Devices (ED) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Study on A Novel Logic-Circuit Implementation Scheme Utilizing Topological Affinity between Decision-Diagram Representation of Logic Functions and Nanowire Network Structures |
| Sub Title (in English) | |
| Keyword(1) | Logic circuit |
| Keyword(2) | nanodevice |
| Keyword(3) | nanowire network |
| Keyword(4) | decision diagram (DD) |
| Keyword(5) | Schottky wrap gate (WPG) |
| 1st Author's Name | Seiya KASAI |
| 1st Author's Affiliation | Graduate School of Information Science & Technology, Hokkaido University:Research Center for Integrated Quantum Electronics, Hokkaido University() |
| 2nd Author's Name | Tatsuya NAKAMURA |
| 2nd Author's Affiliation | Graduate School of Information Science & Technology, Hokkaido University:Research Center for Integrated Quantum Electronics, Hokkaido University |
| 3rd Author's Name | Yuta SHIRATORI |
| 3rd Author's Affiliation | Graduate School of Information Science & Technology, Hokkaido University:Research Center for Integrated Quantum Electronics, Hokkaido University |
| Date | 2007-02-01 |
| Paper # | ED2006-245,SDM2006-233 |
| Volume (vol) | vol.106 |
| Number (no) | 520 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |