| Presentation | 2007/2/2 Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information Yuki YOSHIKAWA, Satoshi OHTAKE, Hideo FUJIWARA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | While design-for-testability (DFT) techniques are generally used in order to reduce test generation complexity, it induces over-testing problems. In general, DFT techniques make a large number of untestable path delay faults (PDFs) testable. However the PDFs which became testable do not affect the circuit performance even if they exist on paths because they were originally untestable. Therefore we consider that testing such PDFs is over-testing. In this work, we reduce the over-testing by identifying false paths using register transfer level information. Our method identifies a subset of false paths and multi-cycle paths within a reasonable time. Experimental results for some RTL benchmark circuits show that the effectiveness of our false path identification method. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Over-testing / delay testing / path delay fault / false path / register-transfer level |
| Paper # | DC2006-87 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2007/2/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reduction in Over-Testing of Delay Faults through False Paths Identification Using RTL Information |
| Sub Title (in English) | |
| Keyword(1) | Over-testing |
| Keyword(2) | delay testing |
| Keyword(3) | path delay fault |
| Keyword(4) | false path |
| Keyword(5) | register-transfer level |
| 1st Author's Name | Yuki YOSHIKAWA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2007/2/2 |
| Paper # | DC2006-87 |
| Volume (vol) | vol.106 |
| Number (no) | 528 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |