| Presentation | 2007/2/2 Test Generation for Transistor Shorts based on Gate-level Yoshinobu HIGAMI, KewalK Saluja, Hiroshi TAKAHASHI, Shin-ya KOBAYASHI, Yuzo TAKAMATSU, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, defects that are not covered by conventional fault models like stuck-at or 2-line bridging fault are increasing. Thus unconventional faults like transistor-level faults must be considered in future LSI tasting. In this article, we propose a test generation method for transistor shorts. The transistor short models used here are constructed by focusing on the output values on faulty gates. The models allow us to generate test patterns by using stuck-at fault tools. Transistor-level tools are never required. Moreover redundant transistor shorts are identified using the list of redundant stuck-at faults. The effectiveness of the proposed method is shown by experimental results for TSCAS bfmchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | test generation / transistor short / combinational circuit / fault simulation |
| Paper # | DC2006-85 |
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| Committee | DC |
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| Conference Date | 2007/2/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Generation for Transistor Shorts based on Gate-level |
| Sub Title (in English) | |
| Keyword(1) | test generation |
| Keyword(2) | transistor short |
| Keyword(3) | combinational circuit |
| Keyword(4) | fault simulation |
| 1st Author's Name | Yoshinobu HIGAMI |
| 1st Author's Affiliation | Course of Electrical and Electronic Engineering and Computer Science, Graduate School of Science and Engineering, Ehime University() |
| 2nd Author's Name | KewalK Saluja |
| 2nd Author's Affiliation | Department of Electrical and Computer Engineering, University of Wisconsin - Madison |
| 3rd Author's Name | Hiroshi TAKAHASHI |
| 3rd Author's Affiliation | Course of Electrical and Electronic Engineering and Computer Science, Graduate School of Science and Engineering, Ehime University |
| 4th Author's Name | Shin-ya KOBAYASHI |
| 4th Author's Affiliation | Course of Electrical and Electronic Engineering and Computer Science, Graduate School of Science and Engineering, Ehime University |
| 5th Author's Name | Yuzo TAKAMATSU |
| 5th Author's Affiliation | Course of Electrical and Electronic Engineering and Computer Science, Graduate School of Science and Engineering, Ehime University |
| Date | 2007/2/2 |
| Paper # | DC2006-85 |
| Volume (vol) | vol.106 |
| Number (no) | 528 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |