Presentation	2007/2/2 Efficiency of compiled-code method in fault simulation for sequential circuits Hideo FUJII, Kenjiro Taniguchi, Seiji KAJIHARA, Xiaoqing WEN,
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Abstract(in English)	As the scale of circuit growth, the time for test pattern generation or fault diagnosis is increasing recently. Especially in sequential circuit, development of speed-up method is needed. In this paper, we propose a speed-up method. It focuses on fault simulation using in them. Our proposed method tries to speed up applying compiled-code method in logic value propagation. Experimental results show the efficiency of our method for sequential benchmark circuits.
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Keyword(in English)	sequential circuit / fault simulation / stuck-at fault / compiled-code method
Paper #	DC2006-82
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Conference Information
Committee	DC
Conference Date	2007/2/2(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Efficiency of compiled-code method in fault simulation for sequential circuits
Sub Title (in English)
Keyword(1)	sequential circuit
Keyword(2)	fault simulation
Keyword(3)	stuck-at fault
Keyword(4)	compiled-code method
1st Author's Name	Hideo FUJII
1st Author's Affiliation	Kyushu Institute of Technology()
2nd Author's Name	Kenjiro Taniguchi
2nd Author's Affiliation	Kyushu Institute of Technology
3rd Author's Name	Seiji KAJIHARA
3rd Author's Affiliation	Kyushu Institute of Technology
4th Author's Name	Xiaoqing WEN
4th Author's Affiliation	Kyushu Institute of Technology
Date	2007/2/2
Paper #	DC2006-82
Volume (vol)	vol.106
Number (no)	528
Page	pp.pp.-
#Pages	6
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