| Presentation | 2007-01-26 Design and Implementation of the 4-b Bit-Slice Adder using SFQ Circuits Hee-joung PARK, Yuki YAMANASHI, Nobuyuki YOSHIKAWA, Masamitsu TANAKA, Akira FUJIMAKI, Hirotaka TERAI, Shinichi YOROZU, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, a lot of researches on designing digital circuits by using SFQ logic circuits have been carried out extensively. We have been developing SFQ microprocessors based on the CORE architecture. In our SFQ microprocessor design, a bit-serial architecture, where the width of the data processed at the same time is 1-bit, has been used up to now to simplify the hardware complexity. In order to increase the performance of the microprocessor, however, we have to increase the width of the data processed at the same time, i.e. bit-slice width. In this paper, we present an architecture of bit-slice adder. In the proposed bit-slice adder, a logarithmic carry look-ahead adder architecture (CLA) was adapted to generate the carries, where the carries generated in the bit-slice data are fed back into the following bit-slice data internally to increase the throughput of the operation. We will show dependences of the operating time and the hardware cost of the bit-slice adder on the bit-slice width. We have also implemented a 4b bit-slice adder using SRL 2.5kA/cm^2 niobium standard process, and demonstrated its high-speed operation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SFQ logic circuit / bit-slice adder / adder / CORE architecture / carry look-ahead adder |
| Paper # | SCE2006-32 |
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| Conference Information | |
| Committee | SCE |
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| Conference Date | 2007/1/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Superconductive Electronics (SCE) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implementation of the 4-b Bit-Slice Adder using SFQ Circuits |
| Sub Title (in English) | |
| Keyword(1) | SFQ logic circuit |
| Keyword(2) | bit-slice adder |
| Keyword(3) | adder |
| Keyword(4) | CORE architecture |
| Keyword(5) | carry look-ahead adder |
| 1st Author's Name | Hee-joung PARK |
| 1st Author's Affiliation | Faculty of Engineering, Yokohama National University() |
| 2nd Author's Name | Yuki YAMANASHI |
| 2nd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 3rd Author's Name | Nobuyuki YOSHIKAWA |
| 3rd Author's Affiliation | Faculty of Engineering, Yokohama National University |
| 4th Author's Name | Masamitsu TANAKA |
| 4th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 5th Author's Name | Akira FUJIMAKI |
| 5th Author's Affiliation | Department of Quantum Engineering, Nagoya University |
| 6th Author's Name | Hirotaka TERAI |
| 6th Author's Affiliation | NICT |
| 7th Author's Name | Shinichi YOROZU |
| 7th Author's Affiliation | NEC |
| Date | 2007-01-26 |
| Paper # | SCE2006-32 |
| Volume (vol) | vol.106 |
| Number (no) | 503 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |