| Presentation | 2007-01-18 Analysis of design architecture of ePLX (embedded Programmable Logic matriX) and Evaluation of circuit mapping Tomoo Hishida, Kouta Ishibashi, Shun Kimura, Naoki Okuno, Mitsutaka Matsumoto, Hirofumi Nakano, Takenobu Iwao, Yoshihiro Okuno, Kazutami Arimoto, Tomonori Izumi, Takeshi Fujino, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, non-recurring engineering costs (NREs), including cost of mask-sets, and engineering design efforts are critical problems in a small-volume SoC(System on a Chip) manufacturing. FPGAs are used for some electrical products, but FPGAs still have lower performance and higher chip-cost than SoC. In this paper, we propose ePLX(embedded Programmable Logic matriX) that is embedded in SoC. Application-specific or customers-specific logic function in SoC can be changed using ePLX. The ePLX architecture is based on the programmable local-clusters, which are composed of two input Look-Up-Table(LUT) matrix and the D-FlipFlops on the matrix side. The hierarchical wiring resources are located between the local-clusters. We demonstrate the ePLX mapping results for sample circuits such as an adder, a multiplier, and a DES encryption circuit, and discuss LUT utilization efficiency. Lastly, we introduce ePLX design flow from HDL code to ePLX configuration data, and experimental results using the mapping tool which is newly-developed for ePLX. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | programmable device / small grain / LUT matrix |
| Paper # | VLD2006-100,CPSY2006-71,RECONF2006-71 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2007/1/11(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of design architecture of ePLX (embedded Programmable Logic matriX) and Evaluation of circuit mapping |
| Sub Title (in English) | |
| Keyword(1) | programmable device |
| Keyword(2) | small grain |
| Keyword(3) | LUT matrix |
| 1st Author's Name | Tomoo Hishida |
| 1st Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University() |
| 2nd Author's Name | Kouta Ishibashi |
| 2nd Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 3rd Author's Name | Shun Kimura |
| 3rd Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 4th Author's Name | Naoki Okuno |
| 4th Author's Affiliation | Faculty of Science and Engineering, Ritsumeikan University |
| 5th Author's Name | Mitsutaka Matsumoto |
| 5th Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University |
| 6th Author's Name | Hirofumi Nakano |
| 6th Author's Affiliation | Renesas Technology Corp. |
| 7th Author's Name | Takenobu Iwao |
| 7th Author's Affiliation | Renesas Technology Corp. |
| 8th Author's Name | Yoshihiro Okuno |
| 8th Author's Affiliation | Renesas Technology Corp. |
| 9th Author's Name | Kazutami Arimoto |
| 9th Author's Affiliation | Renesas Technology Corp. |
| 10th Author's Name | Tomonori Izumi |
| 10th Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University:Faculty of Science and Engineering, Ritsumeikan University |
| 11th Author's Name | Takeshi Fujino |
| 11th Author's Affiliation | Graduate school of Science and Engineering, Ritsumeikan University:Faculty of Science and Engineering, Ritsumeikan University |
| Date | 2007-01-18 |
| Paper # | VLD2006-100,CPSY2006-71,RECONF2006-71 |
| Volume (vol) | vol.106 |
| Number (no) | 458 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |