Presentation 2007-01-18
Optimum Code Scheduling for Clustered VLIW DSP Using Pseudo Boolean Satisfiability
Ryo KOBAYASHI, Yuki MASUI, Nagisa ISHIURA,
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Abstract(in English) This paper proposes a method of finding optimum code scheduling for clustered VLIW DSP TMS320C62x considering the detailed configuration of its datapath and insertion of data transfer operations using Pseudo Boolean Satisfiability (PBSAT). We formulate an optimum code scheduling problem which takes the operand assymmetry for each unit, the capacity of the registerfiles, and the data transfer operations among the main memory and the registerfiles into account. PBSAT is an extension of the Boolean satisfiability problem (SAT) which can deal with linear inequality constraints. It enable us to express the registerfile capacity constraints succinctly and to solve the scheduling problem efficiently.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Pseudo Boolean Satisfiability / clustered VLIW DSP / code scheduling / TMS320C62x
Paper # VLD2006-94,CPSY2006-65,RECONF2006-65
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Committee RECONF
Conference Date 2007/1/11(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Optimum Code Scheduling for Clustered VLIW DSP Using Pseudo Boolean Satisfiability
Sub Title (in English)
Keyword(1) Pseudo Boolean Satisfiability
Keyword(2) clustered VLIW DSP
Keyword(3) code scheduling
Keyword(4) TMS320C62x
1st Author's Name Ryo KOBAYASHI
1st Author's Affiliation Kwansei Gakuin University()
2nd Author's Name Yuki MASUI
2nd Author's Affiliation Kwansei Gakuin University
3rd Author's Name Nagisa ISHIURA
3rd Author's Affiliation Kwansei Gakuin University
Date 2007-01-18
Paper # VLD2006-94,CPSY2006-65,RECONF2006-65
Volume (vol) vol.106
Number (no) 458
Page pp.pp.-
#Pages 5
Date of Issue