Presentation	2007-01-17 On Efficient Cut Enumeration in technology mapping for FPGA Yusuke MATSUNAGA,
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Abstract(in English)	This paper presents a novel efficient algorithm for cut enumeration. Unlike other existing algorithm, the proposed algorithm is based on the top-down algorithm. Strictly Limiting the search space with the proposed idea of terminate condition of cut expansion makes the top-down algorithm efficient. The experimental results show that the proposed algorithm runs in almost linear time to the number of enumerated cuts. The experimental results also show that the bottom-up algorithm does not run in linear time to the number of enumerated cuts but runs in linear time to the product size of cut merging, which is much larger than the number of enumerated cuts in general.
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Keyword(in English)	technology mapping / FPGA / cut enumeration
Paper #	VLD2006-93,CPSY2006-64,RECONF2006-64
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Conference Information
Committee	RECONF
Conference Date	2007/1/10(1days)
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Paper Information
Registration To	Reconfigurable Systems (RECONF)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	On Efficient Cut Enumeration in technology mapping for FPGA
Sub Title (in English)
Keyword(1)	technology mapping
Keyword(2)	FPGA
Keyword(3)	cut enumeration
1st Author's Name	Yusuke MATSUNAGA
1st Author's Affiliation	Faculty of Information Science and Electorical Engineering, Graduate School of Kyushu University()
Date	2007-01-17
Paper #	VLD2006-93,CPSY2006-64,RECONF2006-64
Volume (vol)	vol.106
Number (no)	457
Page	pp.pp.-
#Pages	6
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