Presentation	2007-01-17 Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the effect of Carrier Velocity Saturation Noboru ISHIHARA,
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Abstract(in English)	One of the interesting MOSFET characteristics is the effect of carrier velocity saturation (CVS) on the drain current. In the CVS region, the transconductance becomes constant independent both of the gate and the drain voltage. In this paper, RF CMOS amplifier design technique using the CVS region has been proposed. By setting the FET gate bias to the power supply voltage (Vdd), stable operation against Vdd variations can be achieved with a simple circuit configuration. By using this, a 5GHz amplifier has been designed and fabricated by using 0.18μm CMOS process technology. The chip has been operated with a gain variation less than 1dB having a peak gain of 13.5dB when Vdd has been varied from 1.2 to 2.9V.
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Keyword(in English)	RF-CMOS / Amplifiers / Gate bias circuits / Carrier velocity saturation
Paper #	ED2006-201,MW2006-154
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Committee	MW
Conference Date	2007/1/10(1days)
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Registration To	Microwaves (MW)
Language	JPN
Title (in Japanese)	(See Japanese page)
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Title (in English)	Vdd Gate Biasing RF CMOS Amplifier Design Technique Based on the effect of Carrier Velocity Saturation
Sub Title (in English)
Keyword(1)	RF-CMOS
Keyword(2)	Amplifiers
Keyword(3)	Gate bias circuits
Keyword(4)	Carrier velocity saturation
1st Author's Name	Noboru ISHIHARA
1st Author's Affiliation	Gunma University, Graduate School of Engineering()
Date	2007-01-17
Paper #	ED2006-201,MW2006-154
Volume (vol)	vol.106
Number (no)	460
Page	pp.pp.-
#Pages	6
Date of Issue