Presentation 2006-12-15
Hardware-oriented Flow Managed Buffer Control Mechanism
Yusuke SHINOHARA, Hideki TODE, Koso MURAKAMI,
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Abstract(in English) Today's IP network has trouble realizing QoS guarantee for each flow because the Best-Effort service is provided mainly. Therefore, routers need to equip some control mechanisms which can provide high-speed and high-scalability. So far, we have proposed a new buffer management scheme, called Dual Metrics Fair Queueing (DMFQ), whose throughput is 6.8 Gbps, and High Throughput DMFQ (HTDMFQ), whose throughput is 10.2 Gbps. However, DMFQ and HTDMFQ might not provide enough high performance for newly emerging future networks. In this paper, we extend the existing DMFQs to achieve higher throughput.
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Keyword(in English) router / packet discarding control / high-speed processing / hardware design
Paper # NS2006-144
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Committee NS
Conference Date 2006/12/7(1days)
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Registration To Network Systems(NS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Hardware-oriented Flow Managed Buffer Control Mechanism
Sub Title (in English)
Keyword(1) router
Keyword(2) packet discarding control
Keyword(3) high-speed processing
Keyword(4) hardware design
1st Author's Name Yusuke SHINOHARA
1st Author's Affiliation Department of Information Networking, Osaka University()
2nd Author's Name Hideki TODE
2nd Author's Affiliation Department of Information Networking, Osaka University
3rd Author's Name Koso MURAKAMI
3rd Author's Affiliation Department of Information Networking, Osaka University
Date 2006-12-15
Paper # NS2006-144
Volume (vol) vol.106
Number (no) 418
Page pp.pp.-
#Pages 6
Date of Issue