Presentation 2006-12-15
Architecting of TOPSTREAM^ MPEG-4 Heterogeneous Multi-Core for Video Codec
Yukoh Matsumoto,
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Abstract(in English) One of the complex and power constrained applications of recent SoC is a real-time multimedia processing on battery-driven information appliances. For example, CIF (352×288 pel) size video codec at 15 fps with MPEG-4 Simple Profile requires about 3,000MIPS on general purpose processors. The energy efficiency requirement is around 30MIPS/mW since the power budget of application processor for cell phones is limited to less than 100mW. In addition, because of quick increase of LCD size and migration to newer coding standards such as H.264, etc., scalability and flexibility of SoC design with re-usability of not only the hardware cores but also the software modules becomes very crucial. The scalable Multi-Core platform based SoC IP implementation of MPEG-4 and similar pixel block based image coding is TOPSTREAM^ MPEG-4. It provides 2,997MIPS at 81MHz, and the power estimation based on simulation shows only 74.1mW.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Multi-Core / Processor / SoC / MPEG-4 / SIMD
Paper # ICD2006-169
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Committee ICD
Conference Date 2006/12/7(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecting of TOPSTREAM^ MPEG-4 Heterogeneous Multi-Core for Video Codec
Sub Title (in English)
Keyword(1) Multi-Core
Keyword(2) Processor
Keyword(3) SoC
Keyword(4) MPEG-4
Keyword(5) SIMD
1st Author's Name Yukoh Matsumoto
1st Author's Affiliation TOPS Systems Corp.()
Date 2006-12-15
Paper # ICD2006-169
Volume (vol) vol.106
Number (no) 425
Page pp.pp.-
#Pages 6
Date of Issue