Presentation	2006-12-15 Analysis of Mismatch Characteristics on Analog CMOS Circuit Takeshi KIDA, Shin'ichi OHKAWA, Hiroo MASUDA,
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Abstract(in English)	In sub-100-nm device, mismatch characteristics of threshold voltage and drain current have been degraded. This phenomenon causes variation of timing delay in digital SOC design. On the other hand, mixed signal LSI with analog circuits is expected to suffer from the mismatch-effects much compared with digital ones. This paper firstly reports analog CMOS mismatch characterization. We propose a simulation method and analytical modeling on the mismatch behavior, and verified its key features of sub-100nm analog circuit mismatch design
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Keyword(in English)	Analog CMOS / Mismatch / Simulation / Modeling
Paper #	ICD2006-160
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Conference Information
Committee	ICD
Conference Date	2006/12/7(1days)
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Registration To	Integrated Circuits and Devices (ICD)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	Analysis of Mismatch Characteristics on Analog CMOS Circuit
Sub Title (in English)
Keyword(1)	Analog CMOS
Keyword(2)	Mismatch
Keyword(3)	Simulation
Keyword(4)	Modeling
1st Author's Name	Takeshi KIDA
1st Author's Affiliation	Renesas Technology Corp.()
2nd Author's Name	Shin'ichi OHKAWA
2nd Author's Affiliation	Renesas Technology Corp.
3rd Author's Name	Hiroo MASUDA
3rd Author's Affiliation	Renesas Technology Corp.
Date	2006-12-15
Paper #	ICD2006-160
Volume (vol)	vol.106
Number (no)	425
Page	pp.pp.-
#Pages	6
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