Presentation 2006-12-14
A Current mode high speed pipeline ADC using 90nm CMOS
Ryota AKEYAMA, Atsushi IWATA,
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Abstract(in English) In this report, we propose a low power 8bit 500MS/s pipeline ADC for implementing with scaled CMOS devices, and we designed a test chip using a 90nm CMOS technology with ADC performance of 8bit 500MS/s at 1V supply voltage. We utilize current mode circuit mainly consisting of current mirror circuits. Digital calibration and redundant structure reduce non-linearity of ADC due to device mismatch of scaled devices. Open-loop amplifier circuit structure prevents ADC circuit from circuit complexity and reduces power consumption. By using these circuit techniques, we have gotten prospects for achieving 42mW power consumption in analog circuit.
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Keyword(in English) pipeline / current mode / digital calibration / 90nmCMOS
Paper # ICD2006-145
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Committee ICD
Conference Date 2006/12/7(1days)
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Registration To Integrated Circuits and Devices (ICD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Current mode high speed pipeline ADC using 90nm CMOS
Sub Title (in English)
Keyword(1) pipeline
Keyword(2) current mode
Keyword(3) digital calibration
Keyword(4) 90nmCMOS
1st Author's Name Ryota AKEYAMA
1st Author's Affiliation Graduate School of Advanced Sciences of Matter, Hiroshima University()
2nd Author's Name Atsushi IWATA
2nd Author's Affiliation Graduate School of Advanced Sciences of Matter, Hiroshima University
Date 2006-12-14
Paper # ICD2006-145
Volume (vol) vol.106
Number (no) 425
Page pp.pp.-
#Pages 6
Date of Issue