| Presentation | 2006-11-13 Fast Signal Generations of the Logistic Map employing 128 bit Fixed Point Calculation (FPGA) (I) Atsushi HAMA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Integrated Circuits generating PN signals by 128 bit fixed point calculation of the Logistic map were implemented on FPGA. Fast signal generations of 18Gbps were realized by employing pipe-line structure. 256bit PN signals were scrambled each other and it was observed that successive 0 or 1 distributions were exponential (length of chaotic states～10^<21>bit). |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Fixed Point Calculation / FPGA / Logistic Map / Fast Signal Generations / Chaotic States / Y_ |
| Paper # | NLP2006-66 |
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| Conference Information | |
| Committee | NLP |
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| Conference Date | 2006/11/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Nonlinear Problems (NLP) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Fast Signal Generations of the Logistic Map employing 128 bit Fixed Point Calculation (FPGA) (I) |
| Sub Title (in English) | |
| Keyword(1) | Fixed Point Calculation |
| Keyword(2) | FPGA |
| Keyword(3) | Logistic Map |
| Keyword(4) | Fast Signal Generations |
| Keyword(5) | Chaotic States |
| Keyword(6) | Y_ |
| 1st Author's Name | Atsushi HAMA |
| 1st Author's Affiliation | Nagano Prefecture General Industrial Technology Center() |
| Date | 2006-11-13 |
| Paper # | NLP2006-66 |
| Volume (vol) | vol.106 |
| Number (no) | 344 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |