| Presentation | 2006-11-21 An Improvement Method of the Budget Free Design Method for 100M Tr. Circuits Yuichi NAKAMURA, Mitusru TAGATA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper describes an improvement of the budgeting free hierarchical design method which is eliminating the need to budget the propagation time. The budgeting in hierarchical design partitions the propagation time along to the path between any two flip-flops (FFs) in different hierarchical blocks into three parts: from a flip-flop (FF) to the border of the block containing that FF, from the border of that block to the border of the block containing the other FF, and from the border of that block to the other FF. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. The conventional budgeting-free design method makes the large top-level area, 20% in the total area, by the boarder moving method. In this paper, we propose the making the new hierarchical blocks in the top level to reduce the area of top level. In the experimental results, we confirm the 5% circuits in the total area, are moved to the new hierarchal blocks. This means the proposed method can be applied for 100M Tr. circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | VLSI / Hierarchal Design / Layout / Budgeting |
| Paper # | CAS2006-60,CST2006-36 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2006/11/14(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Improvement Method of the Budget Free Design Method for 100M Tr. Circuits |
| Sub Title (in English) | |
| Keyword(1) | VLSI |
| Keyword(2) | Hierarchal Design |
| Keyword(3) | Layout |
| Keyword(4) | Budgeting |
| 1st Author's Name | Yuichi NAKAMURA |
| 1st Author's Affiliation | Media and Information Research Labs.() |
| 2nd Author's Name | Mitusru TAGATA |
| 2nd Author's Affiliation | NEC Software Hokuriku |
| Date | 2006-11-21 |
| Paper # | CAS2006-60,CST2006-36 |
| Volume (vol) | vol.106 |
| Number (no) | 366 |
| Page | pp.pp.- |
| #Pages | 5 |
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