| Presentation | 2006-11-29 LSSD at speed scan test and Source synchronous DDR interface test by 1149 using on chip PLL Toshihiko Yokota, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | High speed scan-based test using on chip PLL has been developed in IBMASIC based on level sensitive scan design (LSSD) in order to improve shipped module quality. Source-synchronous double data rate interface was found to be testable at full function speed via IEEE1149 interface in a similar way and it's implementation has been investigated. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High speed scan test / On chip PLL / AC test / IEEE1149 / Double data rate / Source synchronous |
| Paper # | VLD2006-71,DC2006-58 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2006/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | LSSD at speed scan test and Source synchronous DDR interface test by 1149 using on chip PLL |
| Sub Title (in English) | |
| Keyword(1) | High speed scan test |
| Keyword(2) | On chip PLL |
| Keyword(3) | AC test |
| Keyword(4) | IEEE1149 |
| Keyword(5) | Double data rate |
| Keyword(6) | Source synchronous |
| 1st Author's Name | Toshihiko Yokota |
| 1st Author's Affiliation | TCS, IBM Japan() |
| Date | 2006-11-29 |
| Paper # | VLD2006-71,DC2006-58 |
| Volume (vol) | vol.106 |
| Number (no) | 388 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |