| Presentation | 2006-11-29 A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework Yukihide KOHIRA, Atsushi TAKAHASHI, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Under the assumption that the clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period might be reduced by register relocation which maintains the circuit behavior and topology. But if the minimum feasible clock period is reduced, then the number of registers tends to be increased. In this paper, we propose a gate-level register relocation method that reduces the number of registers while keeping the target clock period. In experiments, the proposed method reduces the number of registers in the practical time in most circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | generalized-synchronous framework / register relocation / retiming |
| Paper # | VLD2006-70,DC2006-57 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
|---|---|
| Conference Date | 2006/11/22(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework |
| Sub Title (in English) | |
| Keyword(1) | generalized-synchronous framework |
| Keyword(2) | register relocation |
| Keyword(3) | retiming |
| 1st Author's Name | Yukihide KOHIRA |
| 1st Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology() |
| 2nd Author's Name | Atsushi TAKAHASHI |
| 2nd Author's Affiliation | Department of Communications and Integrated Systems, Tokyo Institute of Technology |
| Date | 2006-11-29 |
| Paper # | VLD2006-70,DC2006-57 |
| Volume (vol) | vol.106 |
| Number (no) | 388 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |