Presentation 2006-11-29
Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI
Yosuke TAKAHASHI, Atsushi TAKAHASHI,
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Abstract(in English) The reduction of peak power consumption of LSI is required to reduce the instability of gate operation, the delay increase, the noise, and etc. It is possible to reduce the peak power consumption by clock scheduling because it controls the switching timings of combinational logic elements. In this paper, we propose a clock scheduling approach to smooth the power wave for peak power reduction. The circuits with clock schedule obtained by the proposed method and the previous method are simulated by HSPICE and compared. In the result, the validity of the proposed method is shown on three of four circuits.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) clock-scheduling / general-synchronous circuit / peak power / power estimation
Paper # VLD2006-69,DC2006-56
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Committee VLD
Conference Date 2006/11/22(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Power Wave Smoothing by Clock Scheduling for Peak Power Reduction in LSI
Sub Title (in English)
Keyword(1) clock-scheduling
Keyword(2) general-synchronous circuit
Keyword(3) peak power
Keyword(4) power estimation
1st Author's Name Yosuke TAKAHASHI
1st Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology()
2nd Author's Name Atsushi TAKAHASHI
2nd Author's Affiliation Department of Communications and Integrated Systems, Tokyo Institute of Technology
Date 2006-11-29
Paper # VLD2006-69,DC2006-56
Volume (vol) vol.106
Number (no) 388
Page pp.pp.-
#Pages 6
Date of Issue