Presentation 2006-11-02
RSFQ LSI circuit design approach
Irina Kataeva, Samuel Intiso, Elena Tolkacheva, Anna Kidiyarova-Shevchenko,
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Abstract(in English) We present the methodology and tools developed to design large scale RSFQ circuits. The approach is based on the standard cell library, rsfq65. The design flow includes the construction of the schematic using standard cell library, simulations and inter-cell delay optimization in VHDL. In order to simplify and improve layout design we use standard Cadence tools such as Design Rule Checker (DRC) and Layout Versus Schematic checker (LVS) as well as developed parametric cell library (pcell) and bias current extractor (ERC).
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Keyword(in English) RSFQ / standard cell library / time-delay optimization / VHDL / Cadence
Paper # SCE2006-26
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Conference Information
Committee SCE
Conference Date 2006/10/26(1days)
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Registration To Superconductive Electronics (SCE)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) RSFQ LSI circuit design approach
Sub Title (in English)
Keyword(1) RSFQ
Keyword(2) standard cell library
Keyword(3) time-delay optimization
Keyword(4) VHDL
Keyword(5) Cadence
1st Author's Name Irina Kataeva
1st Author's Affiliation Microtechnology and Nanoscience Department, Chalmers University of Technology()
2nd Author's Name Samuel Intiso
2nd Author's Affiliation Microtechnology and Nanoscience Department, Chalmers University of Technology
3rd Author's Name Elena Tolkacheva
3rd Author's Affiliation Microtechnology and Nanoscience Department, Chalmers University of Technology
4th Author's Name Anna Kidiyarova-Shevchenko
4th Author's Affiliation Microtechnology and Nanoscience Department, Chalmers University of Technology
Date 2006-11-02
Paper # SCE2006-26
Volume (vol) vol.106
Number (no) 334
Page pp.pp.-
#Pages 6
Date of Issue