| Presentation | 2006-11-30 Delay Optimized Technology Mapping for Variable Grain Logic Cell Hideaki NAKAYAMA, Ryoichi YAMAGUCHI, Motoki AMAGASAKI, Kazunori MATSUYAMA, Masahiro IIDA, Toshinori SUEYOSHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The architecture of reconfigurable logic device are classified into coarse-grain and fine-grain by granularity of basic logic cell. However, Since operation grain of both methods which are fixed, they can exercise performance only in the application that is suitable for structure. To solve this problem, we propose new logic block architecture is called VGLC. The VGLC is consisted of a HC (Hybrid Cell) which has full adder and several memory, and it can implements equivalent function of 4-bit Ripple Carry Adder and 2-4LUT. In This paper, We developed VGLC-HeteroMap based on HeteroMap which is a technology mapping tool developed in UCLA to perform technology mapping for VGLC. When we performed technology mapping with a benchmark circuit, it can reduced an average of 38.6% of critical path delay and an average of 47.1% of configuration bits compared to 4-LUT. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic / technology mapping / granularity |
| Paper # | RECONF2006-55 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Delay Optimized Technology Mapping for Variable Grain Logic Cell |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic |
| Keyword(2) | technology mapping |
| Keyword(3) | granularity |
| 1st Author's Name | Hideaki NAKAYAMA |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Ryoichi YAMAGUCHI |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Motoki AMAGASAKI |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Kazunori MATSUYAMA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Masahiro IIDA |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 6th Author's Name | Toshinori SUEYOSHI |
| 6th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2006-11-30 |
| Paper # | RECONF2006-55 |
| Volume (vol) | vol.106 |
| Number (no) | 394 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |