Presentation 2006-11-30
Area-Efficient Reconfigurable Architecture for Media Processing
Kazuma TAKAHASHI, Yukio MITSUYAMA, Takao ONOYE, Isao SHIRAKAWA,
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Abstract(in English) Various reconfigurable architectures have been proposed in accordance with the aim of high performance, high flexibility, and low power consumption. The most serious problem of conventional reconfigurable architectures is a large hardware cost due to the excessive flexibility. In this report, we propose an area-efficient reconfigurable architecture dedicated for media processing. Evaluation of MPEG-2 decoder, H.263 decoder, and MPEG-4 decoder on the proposed reconfigurable system has been performed. Implemented reslts show that multi-standard decoder can be implemented in the proposed reconfigurable system with 1.1×1.2mm^2 in a 90nm CMOS technology.
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Keyword(in English) Dynamically reconfiguration / Area-efficient / Media processing
Paper # RECONF2006-51
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Committee RECONF
Conference Date 2006/11/23(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Area-Efficient Reconfigurable Architecture for Media Processing
Sub Title (in English)
Keyword(1) Dynamically reconfiguration
Keyword(2) Area-efficient
Keyword(3) Media processing
1st Author's Name Kazuma TAKAHASHI
1st Author's Affiliation Graduate School of Information Science and Technology, Osaka University()
2nd Author's Name Yukio MITSUYAMA
2nd Author's Affiliation Graduate School of Information Science and Technology, Osaka University
3rd Author's Name Takao ONOYE
3rd Author's Affiliation Graduate School of Information Science and Technology, Osaka University
4th Author's Name Isao SHIRAKAWA
4th Author's Affiliation Graduate School of Applied Informatics, University of Hyogo
Date 2006-11-30
Paper # RECONF2006-51
Volume (vol) vol.106
Number (no) 394
Page pp.pp.-
#Pages 6
Date of Issue