Presentation | 2006-11-30 Consideration about Reconfigurable Architecture based on Digit Serial Arithmetics Kazuya TANIGAWA, Tetsuo HIRONAKA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In our research. we have considered a reconfigurable architecture which can map a large virtual circuit information to small reconfigurable devices by introducing digit serial arithmetic. In this paper, we describe merits about such an architecture, then we consider the reconfigurable execution units and routing structure of the architecture. Further, we evaluate how many reconfigurable units was used over all reconfigurable units in a condition on DCT program is mapped. The usage of reconfigurable units in this evaluation is 74%. From this result, we can say that our approach has some advantages on improving current reconfigurable architectures. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | reconfigurable architecture / dynamic reconfiguration / digit serial arithmetics |
Paper # | RECONF2006-49 |
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Committee | RECONF |
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Conference Date | 2006/11/23(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Consideration about Reconfigurable Architecture based on Digit Serial Arithmetics |
Sub Title (in English) | |
Keyword(1) | reconfigurable architecture |
Keyword(2) | dynamic reconfiguration |
Keyword(3) | digit serial arithmetics |
1st Author's Name | Kazuya TANIGAWA |
1st Author's Affiliation | Department of Computer Engineering, Hiroshima City University() |
2nd Author's Name | Tetsuo HIRONAKA |
2nd Author's Affiliation | Department of Computer Engineering, Hiroshima City University |
Date | 2006-11-30 |
Paper # | RECONF2006-49 |
Volume (vol) | vol.106 |
Number (no) | 394 |
Page | pp.pp.- |
#Pages | 6 |
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