| Presentation | 2006-11-30 Architecture for Numerical Function Generators Using EVBDDs Shinobu NAGAYAMA, Tsutomu SASAO, Jon T. BUTLER, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents an architecture and a synthesis method for fast and compact numerical function generators (NFGs) for trigonometric, logarithmic, square root, reciprocal, and combinations of these functions. Our NFG partitions a given domain of the function into non-uniform segments, and approximates the given function by a polynomial function for each segment. By using an edge-valued binary decision digram (EVBDD) to realize the non-uniform segmentation, we can implement fast and compact NFGs for a wide range of functions. Implementation results on an FPGA show that: 1) To realize a non-uniform segmentation, our method using EVBDD requires, on average, only 7% of the memory and 40% of the delay time needed by the existing method using multi-terminal BDD (MTBDD); and therefore, 2) our NFG requires, on average, only 38% of the memory and 59% of the delay time needed by the existing NFG using non-uniform segmentation and MTBDD. Our automatic synthesis system generates such fast and compact NFGs quickly. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Edge-valued binary decision diagram (EVBDD) / non-uniform segmentation / piecewise polynomial approximation / numerical function generators (NFGs) / FPGA implementation |
| Paper # | RECONF2006-48 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2006/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Architecture for Numerical Function Generators Using EVBDDs |
| Sub Title (in English) | |
| Keyword(1) | Edge-valued binary decision diagram (EVBDD) |
| Keyword(2) | non-uniform segmentation |
| Keyword(3) | piecewise polynomial approximation |
| Keyword(4) | numerical function generators (NFGs) |
| Keyword(5) | FPGA implementation |
| 1st Author's Name | Shinobu NAGAYAMA |
| 1st Author's Affiliation | Department of Computer Engineering, Hiroshima City University() |
| 2nd Author's Name | Tsutomu SASAO |
| 2nd Author's Affiliation | Department of Computer Science and Electronics, Kyushu Institute of Technology |
| 3rd Author's Name | Jon T. BUTLER |
| 3rd Author's Affiliation | Department of Electrical and Computer Engineering, Naval Postgraduate School |
| Date | 2006-11-30 |
| Paper # | RECONF2006-48 |
| Volume (vol) | vol.106 |
| Number (no) | 394 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |