Presentation | 2006-11-30 Design Method of Radix Converters Using Arithmetic Decompositions (2) Yukihiro IGUCHI, Tsutomu SASAO, Munehiro MATSUURA, |
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Abstract(in English) | In digital signal processing, radixes other than two are often used for high-speed computation. In the computation for finance. decimal numbers are used instead of binary numbers. In such cases, radix converters are necessary. This paper considers design methods for binary to q-nary converters. It introduces a new design technique based on weighted-sum (WS) functions. We compute a WS function for each digit by an LUT cascade and a binary adder, then add adjacent digits with q-nary adders. A 16-bit binary to decimal converter is designed to show the method. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Radix converter / Multiple valued logic / LUT cascades |
Paper # | RECONF2006-47 |
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Committee | RECONF |
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Conference Date | 2006/11/23(1days) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Design Method of Radix Converters Using Arithmetic Decompositions (2) |
Sub Title (in English) | |
Keyword(1) | Radix converter |
Keyword(2) | Multiple valued logic |
Keyword(3) | LUT cascades |
1st Author's Name | Yukihiro IGUCHI |
1st Author's Affiliation | Department of Computer Scienece, Meiji University() |
2nd Author's Name | Tsutomu SASAO |
2nd Author's Affiliation | Department of Computer Scienece and Electronics, Kyushu Institute of Technology |
3rd Author's Name | Munehiro MATSUURA |
3rd Author's Affiliation | Department of Computer Scienece and Electronics, Kyushu Institute of Technology |
Date | 2006-11-30 |
Paper # | RECONF2006-47 |
Volume (vol) | vol.106 |
Number (no) | 394 |
Page | pp.pp.- |
#Pages | 6 |
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