| Presentation | 2006-11-30 Development and evaluation of virus check system using FPGA Yukari ISHIDA, Yosuke IIJIMA, Eiichi TAKAHASHI, Tatsumi FURUYA, Tetsuya HIGUCHI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Last year we proposed a method of executing virus checking with a Field Programmable Gate Array (FPGA), which is a reconfigurable hardware device. Our method involves inserting a virus check system in between the computer to be protected and the network and prevents virus attacks and diffusions. With this approach, we can realize (1) high-speed virus checks while avoiding communication bottlenecks, (2) a safer security measure that blocks viruses from invading the protected computer, and (3) a universal security system that can be used with any type of computer. This paper reports on the functions of the completed virus check system (automatic downloads of the latest virus information, automatic generation of matching circuit, and automatic FPGA reconfiguration) and presents performance evaluation results. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network Security / Computer Virus / Reconfigurable Hardware / FPGA / Virus Check / Hardware Matching / 10G Ethernet |
| Paper # | RECONF2006-45 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2006/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development and evaluation of virus check system using FPGA |
| Sub Title (in English) | |
| Keyword(1) | Network Security |
| Keyword(2) | Computer Virus |
| Keyword(3) | Reconfigurable Hardware |
| Keyword(4) | FPGA |
| Keyword(5) | Virus Check |
| Keyword(6) | Hardware Matching |
| Keyword(7) | 10G Ethernet |
| 1st Author's Name | Yukari ISHIDA |
| 1st Author's Affiliation | Toho University() |
| 2nd Author's Name | Yosuke IIJIMA |
| 2nd Author's Affiliation | University of Tsukuba |
| 3rd Author's Name | Eiichi TAKAHASHI |
| 3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology |
| 4th Author's Name | Tatsumi FURUYA |
| 4th Author's Affiliation | Toho University |
| 5th Author's Name | Tetsuya HIGUCHI |
| 5th Author's Affiliation | National Institute of Advanced Industrial Science and Technology |
| Date | 2006-11-30 |
| Paper # | RECONF2006-45 |
| Volume (vol) | vol.106 |
| Number (no) | 394 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |