| Presentation | 2006-11-30 A Design of AES S-BOX circuit for DPA countermeasure Minoru SASAKI, Keisuke IWAI, Takakazu KUROKAWA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Various methods about the design of the S-BOX circuit of AES (Advanced Encryption Standard) have been proposed. Especially, it is effective for a compact cryptsystem to design S-BOX with composite field, because its circuit scale can be greatly reduced. Tamper resistance is nessesary for a secure system in recent years, so that several random masking methods for S-BOX circuit have been proposed as DPA (Differential Power Analysis) countermeasures. In this research, authors propose a S-BOX circuit in AES adapting composite field based on MRSL (Modified RSL) as a random masking method at the primitive gate level, and its implememtation on FPGA (Virtex1000) is also shown. Moreover, other countermeasures such as Masked-AND method poroposed by Trichina, RSL (Random Switching Logic) method proposed by Suzuki, and a method proposed by Morioka are implememeted on FPGA and compared on the stand point of DPA tolerance. As a result, it was confirmed that MRSL can use LUT efficiently, and can be the most effective DPA countermeasure on the standpoint of circuit scale, and simple design. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | DPA / Shide-channel attack / RSL / FPGA |
| Paper # | RECONF2006-44 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2006/11/23(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design of AES S-BOX circuit for DPA countermeasure |
| Sub Title (in English) | |
| Keyword(1) | DPA |
| Keyword(2) | Shide-channel attack |
| Keyword(3) | RSL |
| Keyword(4) | FPGA |
| 1st Author's Name | Minoru SASAKI |
| 1st Author's Affiliation | Department of Computer Science, National Defense Academy() |
| 2nd Author's Name | Keisuke IWAI |
| 2nd Author's Affiliation | Department of Computer Science, National Defense Academy |
| 3rd Author's Name | Takakazu KUROKAWA |
| 3rd Author's Affiliation | Department of Computer Science, National Defense Academy |
| Date | 2006-11-30 |
| Paper # | RECONF2006-44 |
| Volume (vol) | vol.106 |
| Number (no) | 394 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |