| Presentation | 2006-11-28 Test Scheduling for SoGs with Built-In Self-Repairable Memory Cores Yusuke FUKUDA, Tomokazu YONEDA, Hideo FUJIWARA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents a power-constrained test scheduling mehtod for SoCs with built-in self repairable memories which are tested the following three stages: 1) test, 2) diagnosis/repair and 3) re-test. The proposed method can acheive efficient and effective scheduling by considering that it is not necessary to test the three stages of each core consecutively as long as they are tested in correct order. Moreover, by using the concept of abort-on-fail which means that the test is aborted as soon as a fault is detected, we can reduce expected test time. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | System-on-Chip / Built-In Self-Repair / Power Constraints / Test Scheduling |
| Paper # | VLD2006-61,DC2006-48 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2006/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test Scheduling for SoGs with Built-In Self-Repairable Memory Cores |
| Sub Title (in English) | |
| Keyword(1) | System-on-Chip |
| Keyword(2) | Built-In Self-Repair |
| Keyword(3) | Power Constraints |
| Keyword(4) | Test Scheduling |
| 1st Author's Name | Yusuke FUKUDA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Tomokazu YONEDA |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2006-11-28 |
| Paper # | VLD2006-61,DC2006-48 |
| Volume (vol) | vol.106 |
| Number (no) | 390 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |