| Presentation | 2006-11-28 Formal Verification Method for Arithmetic Circuits and Its Evaluation Yuki WATANABE, Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper presents the formal design of arithmetic circuits based on arithmetic description language called ARITH. By using ARITH, we can describe a wide variety of arithmetic algorithms including those using unconventional number systems. The functionality of arithmetic algorithms in ARITH can be formally verified using formula manipulation methods. In this paper, we compare the proposed formula-based method with the conventional *BMD-based method, and demonstrate that the combination of the two methods enables to verify arithmetic circuits in an efficient way. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | arithmetic algorithms / formal verification / datapaths / hardware description language |
| Paper # | VLD2006-54,DC2006-41 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2006/11/21(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Formal Verification Method for Arithmetic Circuits and Its Evaluation |
| Sub Title (in English) | |
| Keyword(1) | arithmetic algorithms |
| Keyword(2) | formal verification |
| Keyword(3) | datapaths |
| Keyword(4) | hardware description language |
| 1st Author's Name | Yuki WATANABE |
| 1st Author's Affiliation | Graduate School of Information Sciences Tohoku University() |
| 2nd Author's Name | Naofumi HOMMA |
| 2nd Author's Affiliation | Graduate School of Information Sciences Tohoku University |
| 3rd Author's Name | Takafumi AOKI |
| 3rd Author's Affiliation | Graduate School of Information Sciences Tohoku University |
| 4th Author's Name | Tatsuo HIGUCHI |
| 4th Author's Affiliation | Department of Electronic Engineering, Faculty of Engineering, Tohoku Institute of Technology |
| Date | 2006-11-28 |
| Paper # | VLD2006-54,DC2006-41 |
| Volume (vol) | vol.106 |
| Number (no) | 390 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |