Presentation 2006-11-28
A methodology of generating verification scenarios from specification
Ryosuke OISHI, Akio MATSUDA, Hiroaki IWASHITA, Koichiro TAKAYAMA,
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Abstract(in English) For designing SoC or embedded software, it is required that they have to be verified immediately in the level of specification design. By previous works, verifiers had to write scenarios without automation because the scenarios are generated from specification which is wrote in natural language. In this paper we propose a methodology how to generate verification scenarios fully and automatically, from pre-conditions and post-conditions and constraints in the scenarios by using model-checking tool. Experiment results show that verifications scenarios which fully cover specification are generated in short time.
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Keyword(in English) specification / verification / test / scenario / model checking / UML
Paper # VLD2006-51,DC2006-38
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Conference Date 2006/11/21(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A methodology of generating verification scenarios from specification
Sub Title (in English)
Keyword(1) specification
Keyword(2) verification
Keyword(3) test
Keyword(4) scenario
Keyword(5) model checking
Keyword(6) UML
1st Author's Name Ryosuke OISHI
1st Author's Affiliation Fujitsu Laboratories LTD.()
2nd Author's Name Akio MATSUDA
2nd Author's Affiliation Fujitsu Laboratories LTD.
3rd Author's Name Hiroaki IWASHITA
3rd Author's Affiliation Fujitsu Laboratories LTD.
4th Author's Name Koichiro TAKAYAMA
4th Author's Affiliation Fujitsu Laboratories LTD.
Date 2006-11-28
Paper # VLD2006-51,DC2006-38
Volume (vol) vol.106
Number (no) 390
Page pp.pp.-
#Pages 4
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