Presentation 2006-10-17
Architecture of Hi-speed Network Filtering System
Kenji TODA, Toshihiro KATASHITA, Kazumi SAKAMAKI, Mitsugu NAGOYA, Yasunori TERASHIMA,
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Abstract(in Japanese) (See Japanese page)
Abstract(in English) Information filtering service has become inevitable. This article presented the architecture of URL filtering system which work at over 10Gbps by using FPGA.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Network / URL / hardware filtering / FPGA / 10Gbps / 10GbEther
Paper # DE2006-122,DC2006-29
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Committee DE
Conference Date 2006/10/10(1days)
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Registration To Data Engineering (DE)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Architecture of Hi-speed Network Filtering System
Sub Title (in English)
Keyword(1) Network
Keyword(2) URL
Keyword(3) hardware filtering
Keyword(4) FPGA
Keyword(5) 10Gbps
Keyword(6) 10GbEther
1st Author's Name Kenji TODA
1st Author's Affiliation National Institute of Advanced Industrial Science and Technology()
2nd Author's Name Toshihiro KATASHITA
2nd Author's Affiliation National Institute of Advanced Industrial Science and Technology
3rd Author's Name Kazumi SAKAMAKI
3rd Author's Affiliation Tokyo Metropolitan Industrial Technology Research Institute
4th Author's Name Mitsugu NAGOYA
4th Author's Affiliation DUAXES Corporation
5th Author's Name Yasunori TERASHIMA
5th Author's Affiliation BITS Co., Ltd.
Date 2006-10-17
Paper # DE2006-122,DC2006-29
Volume (vol) vol.106
Number (no) 290
Page pp.pp.-
#Pages 5
Date of Issue