Presentation 2006-10-26
An Analysis on a Tradeoff between Reliability and Performance and a Reliable Cache Architecture for Computer Systems
Makoto SUGIHARA, Tohru ISHIHARA, Kazuaki MURAKAMI,
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Abstract(in English) In this paper, we discuss reliability of a computer system which consists of various IC components. We focus on the difference between SERs of SRAM and DRAM memories and analyze a tradeoff between reliability and performance of a computer system. We also propose reliable cache architectures for both reliability and performance. We introduce reliability and performance modes for reliable cache architectures. Controlling the operation mode of a computer system decreases vulnerability of a computer system under a certain performance constraint. Our experiments show that switching the operation modes of the cache memories affects performance and reliability of a computer system and is effective for tuning its performance and reliability.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Soft Error / Reliability / Performance / Cache Memory
Paper # SIP2006-99,ICD2006-125,IE2006-77
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Committee SIP
Conference Date 2006/10/19(1days)
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Registration To Signal Processing (SIP)
Language ENG
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An Analysis on a Tradeoff between Reliability and Performance and a Reliable Cache Architecture for Computer Systems
Sub Title (in English)
Keyword(1) Soft Error
Keyword(2) Reliability
Keyword(3) Performance
Keyword(4) Cache Memory
1st Author's Name Makoto SUGIHARA
1st Author's Affiliation ISIT()
2nd Author's Name Tohru ISHIHARA
2nd Author's Affiliation System LSI Research Center, Kyushu University
3rd Author's Name Kazuaki MURAKAMI
3rd Author's Affiliation The Department of Informatics, Kyushu University
Date 2006-10-26
Paper # SIP2006-99,ICD2006-125,IE2006-77
Volume (vol) vol.106
Number (no) 314
Page pp.pp.-
#Pages 6
Date of Issue