Presentation 2006-10-27
High-Performance Asynchronous Data Transfer VLSI Based on Multiple-Valued Dual-Rail Encoding
Tomohiro TAKAHASHI, Kazuyasu MIZUSAWA, Takahiro HANYU,
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Abstract(in English) A full-duplex asynchronous communication scheme based on one-phase dual-rail encoding is proposed for on-chip high-speed communication. Since control signals and data from mutual modules are multiplexed using a multi-level dual-rail codeword, full-duplex data transfer without clocks can be realized by using only two wires; one wire per bit. As compared to uni-directional scheme, the increased level of multiple-valued signal is slight because different valid states are assigned on a common codeword. As a result, it is evaluated by using a 0.18-μm CMOS technology that the throughput and energy dissipation of the proposed asynchronous scheme attains a value of 1.18 Gb/s/wire and 0.78 pJ/bit, respectively, at a wire length of 1mm.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Duplex communication / Network-on-chip(NoC) / System-on-a-chip(SoC) / Delay-insensitive
Paper # SIP2006-107,ICD2006-133,IE2006-85
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Conference Date 2006/10/20(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) High-Performance Asynchronous Data Transfer VLSI Based on Multiple-Valued Dual-Rail Encoding
Sub Title (in English)
Keyword(1) Duplex communication
Keyword(2) Network-on-chip(NoC)
Keyword(3) System-on-a-chip(SoC)
Keyword(4) Delay-insensitive
1st Author's Name Tomohiro TAKAHASHI
1st Author's Affiliation Research Institute of Electrical Communication, Tohoku University()
2nd Author's Name Kazuyasu MIZUSAWA
2nd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
3rd Author's Name Takahiro HANYU
3rd Author's Affiliation Research Institute of Electrical Communication, Tohoku University
Date 2006-10-27
Paper # SIP2006-107,ICD2006-133,IE2006-85
Volume (vol) vol.106
Number (no) 317
Page pp.pp.-
#Pages 6
Date of Issue