| Presentation | 2006-10-26 Reducing the Circuit Size of Multipliers Jiunn Jong Edwin TAN, Ryusuke EGAWA, Jubei TADA, Ken-ichi SUZUKI, Gensuke GOTO, Tadao NAKAMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Aiming at reducing the power consumption of future VLSIs, small and fast arithmetic units are required. Since multipliers play an essential role in recent microprocessors, this study focuses on multipliers and discusses the effects of bit slicing technique on the latency and hardware cost. In particular, partial product generation by Booth method, partial product reduction by array and reduction tree, and final addition by a carry-independent adder are examined. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Low-power / Multiplier |
| Paper # | SIP2006-91,ICD2006-117,IE2006-69 |
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| Conference Information | |
| Committee | ICD |
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| Conference Date | 2006/10/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Integrated Circuits and Devices (ICD) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Reducing the Circuit Size of Multipliers |
| Sub Title (in English) | |
| Keyword(1) | Low-power |
| Keyword(2) | Multiplier |
| 1st Author's Name | Jiunn Jong Edwin TAN |
| 1st Author's Affiliation | Graduate School of Information Sciences, Tohoku University() |
| 2nd Author's Name | Ryusuke EGAWA |
| 2nd Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 3rd Author's Name | Jubei TADA |
| 3rd Author's Affiliation | Faculty of Engineering, Yamagata University |
| 4th Author's Name | Ken-ichi SUZUKI |
| 4th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| 5th Author's Name | Gensuke GOTO |
| 5th Author's Affiliation | Faculty of Engineering, Yamagata University |
| 6th Author's Name | Tadao NAKAMURA |
| 6th Author's Affiliation | Graduate School of Information Sciences, Tohoku University |
| Date | 2006-10-26 |
| Paper # | SIP2006-91,ICD2006-117,IE2006-69 |
| Volume (vol) | vol.106 |
| Number (no) | 316 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |